This invention relates to routers used for routing messages between a local area network (LAN) and one or more wide area networks (WANs) and more particularly to a router architecture integrated onto a single silicon chip that is adaptable to a wide variety of network configurations.
A router is essentially a computer dedicated to the task of routing messages between different network protocols and between different networks having similar protocols. The router must contain the necessary input and output connections for linking different network systems together. Routers also have an internal computer architecture and associated control for converting data packets between different network protocols. For example, Ethernet is a widely-used standard for LANs that allows data transfer rates of 10 million bits per second (Mbps). Ethernet can be used to implement bus architecture networks. In contrast, WANs typically implement point-to-point connections and transfer data packets at rates below 1 Mbps.
A variety of different routers and associated router architectures have been developed to support different network configurations. Routers typically include multiple circuit boards connected together in a chassis which typically has a size comparable with the processing box of a personal computer. The cabinet, circuit boards, interface circuitry, etc., used to build a router are expensive and require a substantial amount of assembly time. To reduce the physical size and cost of routers and the amount of time required for assembly, it would be necessary to integrate many of the different router functions onto the same circuit board or processing chip. However, due to the variety of different network configurations and protocols used in different network systems, current router architectures are not capable of adequately supporting a wide variety of network configurations, network protocols and other peripheral devices without considerable cost. For example, routers are typically designed to operate with a given combination of external serial and time division multiplexed data lines. The router may not support the new network configuration if the format of the data stream transmitted over the lines changes or a different combination of external network lines are used.
The time required for a router to convert and route data packets into different network protocols and between different networks depends upon how efficiently data packets are transferred between different router processing elements. However, different amounts of data can be transmitted to the router at any given time from any one of the connected networks. The internal bus architecture in current router architectures have a dedicated bandwidth allocation scheme for processing data packets from each external network connection. However, dedicated bandwidth allocation does not utilize internal bus transactions efficiently for network data packets that may be received or transmitted at variable data rates from each connected network. Thus, router performance can degrade for certain network processing conditions.
Accordingly, a need remains for a router architecture integrated onto a single silicon chip that is adaptable to a wide variety of different network systems and peripheral interfaces while at the same time being adaptable to changing data processing requirements and reducing the overall cost of the router.
A complete router architecture is integrated onto a single silicon chip and includes an internal bus that couples multiple channels to a central processing unit. The channels each have an external interface for connecting to different LAN or WAN lines. Multiple serial channels and an Ethernet channel receive and transmit data packets that are converted between different network packet protocols by the CPU. The serial channels have a novel architecture that allows conversion into one or more time division multiplexed (TDM) channels.
A serial line multiplexer (SLM) provides an external interface for each one of the multiple serial channels. The serial channels each include serial communication controllers (SCCs) and FIFOs for temporarily storing network data packets. A time slot assigner (TSA) is coupled between the SLM and the SCCs and assembles and disassembles data packets transferred in TDM formats such as ISDN. The TSA is programmable to operate with different TDM formats.
A single direct memory access (DMA) controller is coupled to each serial channel and the Ethernet channel and conducts data transfers over the internal router bus. The DMA uses an internal bus bandwidth allocation protocol that can adjust the percentage of bus bandwidth dedicated to each channel. The bus bandwidth allocation protocol increases bandwidth efficiency by varying the number and location of time slots each channel is assigned to match the channel""s bandwidth requirements.
The DMA controller performs block data transfers without alignment restrictions for data start and end points allowing block transfers of packet data to begin and end on any byte boundary. The capability to support non-aligned block transfers of packet data avoids burdening the CPU with time-consuming re-alignment of the packet data to boundaries imposed by a DMA controller.
The SCC also transfers data in either bit direction, most significant bit (MSB) first or least significant bit (LSB) first. The normally CPU-intensive task of bit swapping is then performed by the SCC on-the-fly either while data packets are transferred into memory from a router interface, or as data is moved from memory to the interface.
The DMA controller services multiple transmit and receive interfaces. Each interface can implement data link channels having widely varying requirements for bandwidth and latency. For instance, an Ethernet interface operates at 10 million bits per second (Mbps), while a serial interface may be attached to a user terminal where the max data rate is in the range of 500 bps. The programmable bus bandwidth allocation allows each channel""s portion of the total available bus bandwidth to be individually adjusted. The maximum latency for responding to data in each channel is also adjustable.
The router architecture includes different interface circuitry which is also integrated onto the silicon chip. The interface circuitry allows the router to operate optimally with a wider variety of memory and peripheral devices. The interface circuitry includes a user definable input/output (I/O) circuit with programmable pulse width detection. The user definable I/O circuit provides synchronous and asynchronous interfacing to peripheral devices with different timing constraints. The interface circuitry also includes two UART interface circuits, a PC card controller and an external bus interface.
The router includes a DRAM controller having a programmable timing control circuit that supports memory devices with different timing requirements and selectable memory bank sizes. Thus, the router can operate with a wider variety of memory configurations than current router architectures.
The router is integrated onto a single silicon chip reducing manufacturing and assembly costs while at the same time providing an architecture that operates more efficiently with a wider variety of network configurations and network protocols. The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention which proceeds with reference to the accompanying drawings.